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1 fn6501.1 isl78010 automotive grade tft-lcd power supply the isl78010 is a multiple output regulator for use in all tft-lcd automotive applications. it features a single boost converter with an integrated 2a fet, two positive ldos for v on and v logic generation, and a single negative ldo for v off generation. the boost converter can be programmed to operate in either p-mode for optimal transient response or pi-mode for improved load regulation. the isl78010 includes fault protection for all four channels. once a fault is detec ted on either the v boost , v on or v off channels, the device is latched off until the input supply or en is cycled. if a fault is detected on the v logic channel, the device is latched off until the input supply is cycled. the v logic channel is not affected by the en function. the isl78010 also includes an integrated start-up sequence for v logic , v boost , v off , then v on or for v logic , v off , v boost , and v on . the latter sequence requires a single external transistor. the timing of the start-up sequence is set using an external capacitor. the isl78010 comes in a 32 ld 5x5 tqfp package and is specified for operation over a -40c to +105c temperature range. it is both aec-q100 rated and fully ts16949 compliant. features ? 2a current fet ? 3v to 5v input ? up to 20v boost output ? 1% regulation on boost output ?v logic -v boost -v off -v on or v logic -v off -v boost -v on sequence control ? programmable sequence delay ? fully fault protected ? thermal shutdown ? internal soft-start ? 32 ld 5x5 tqfp packages ? aec-q100 tested ? ts16949 compliant ? pb-free (rohs compliant) applications ? all automotive lcd displays ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl78010anz 78010 anz 32 ld 5x5 tqfp q32.5x5 ISL78010EVAL1Z evaluation board 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). in tersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl78010 . for more information on msl please see techbrief tb363 . pinout isl78010 (32 ld 5x5 tqfp) top view nc drvn sgnd fbl nc drvl nc fbp cint fbb sgnd en vdd pg cdly nc nc nc delb nc lx nc drvp nc vref nc pgnd pgnd pgnd pgnd nc fbn 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 data sheet may 3, 2011 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2007, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn6501.1 may 3, 2011 absolute maxi mum ratings (t a = +25c) thermal information v delb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24v v drvp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36v v drvn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20v v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v v lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24v v drvl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v thermal resistance (typical) (notes 4, 5) ja (c/w) jc (c/w) 32 ld 5x5 tqfp. . . . . . . . . . . . . . . . . . 71 25 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c power dissipation . . . . .see ?typ ical performance curves? (page 5) maximum continuous junction temperature . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient operating temperature . . . . . . . . . . . . . . .-40c to +105c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a . electrical specifications v dd = 5v, v boost = 11v, i load = 200ma, v on = 15v, v off = -5v, v logic = 2.5v, limits over -40c to +105c temperature range, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c. parameter description condition min (note 6) typ max (note 6) unit supply v s supply voltage 35.5 v i s quiescent current enabled, lx not switching 1.7 2.5 ma disabled 750 900 a clock f osc oscillator frequency 900 1000 1100 khz boost v boost boost output range 5.5 20 v v fbb boost feedback voltage t a = +25c 1.192 1.205 1.218 v 1.188 1.205 1.222 v v f_fbb fbb fault trip point 0.9 v v ref reference voltage t a = +25c 1.19 1.215 1.235 v 1.187 1.215 1.238 v d max maximum duty cycle 85 % i lxmax current switch 2.0 a i leak switch leakage current v lx = 16v 10 a r ds(on) switch on-resistance 320 m eff boost efficiency see ?typical performance curves? (page 5) 85 92 % i(v fbb ) feedback input bias current pl mode, v fbb = 1.35v 50 500 na v boost / v in line regulation c int = 4.7nf, i out = 100ma, v in = 3v to 5.5v 0.05 %/v v boost / i boost load regulation - ?p? mode c int pin strapped to v dd , 50ma < i load < 250ma 3% v boost / i boost load regulation - ?pi? mode c int = 4.7nf, 50ma < i o < 250ma 0.1 % isl78010
3 fn6501.1 may 3, 2011 v cint_t cint pl mode select threshold 4.7 4.8 v v on ldo v fbp fbp regulation voltage i drvp = 0.2ma, t a = +25c 1.176 1.2 1.224 v i drvp =0.2ma 1.172 1.2 1.228 v v f_fbp fbp fault trip point v fbp falling 0.82 0.87 0.92 v i fbp fbp input bias current v fbp = 1.35v -250 250 na gmp fbp effective transconductance v drvp = 25v, i drvp = 0.2ma to 2ma 50 ms v on / i(v on )v on load regulation i(v on ) = 0ma to 20ma -0.5 % i drvp drvp sink current max v fbp = 1.1v, v drvp = 25v 2 4ma i l_drvp drvp leakage current v fbp = 1.5v, v drvp = 35v 0.1 5 a v off ldo v fbn fbn regulation voltage i drvn = 0.2ma, t a = +25c 0.173 0.203 0.233 v i drvn =0.2ma 0.171 0.203 0.235 v v f_fbn fnn fault trip point v fbn falling 0.38 0.43 0.48 v i fbn fbn input bias current v fbn = 0.2v -250 250 na gmn fbn effective transconductance v drvn = -6v, i drvn = 0.2ma to 2ma 50 ms v off / i(v off ) v off load regulation i(v off ) = 0ma to 20ma -0.5 % i drvn drvn source current max v fbn = 0.3v, v drvn = -6v 2 4ma i l_drvn drvn leakage current v fbn = 0v, v drvn = -20v 0.1 5 a v logic ldo v fbl fbl regulation voltage i drvl = 1ma, t a = +25c 1.176 1.2 1.224 v i drvl =1ma 1.174 1.2 1.226 v v f_fbl fbl fault trip point v fbl falling 0.82 0.87 0.92 v i fbl fbl input bias current v fbl = 1.35v -500 500 na g ml fbl effective transconductance v drvl = 2.5v, i drvl = 1ma to 8ma 200 ms v logic / i(v logic ) v logic load regulation i(v logic ) = 100ma to 500ma 0.5 % i drvl drvl sink current max v fbl = 1.1v, v drvl = 2.5v 8 16 ma i l_drl i l_drvl v fbl = 1.5v, v drvl = 5.5v 0.1 5 a sequencing t on turn on delay c dly = 0.22f 30 ms t ss soft-start time c dly = 0.22f 2 ms t del1 delay between a vdd and v off c dly = 0.22f 10 ms t del2 delay between v on and v off c dly = 0.22f 17 ms i delb delb pull-down current v delb >0.6v 50 a v delb <0.6v 1.4 ma electrical specifications v dd = 5v, v boost = 11v, i load = 200ma, v on = 15v, v off = -5v, v logic = 2.5v, limits over -40c to +105c temperature range, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter description condition min (note 6) typ max (note 6) unit isl78010
4 fn6501.1 may 3, 2011 fault detection t fault fault time out c dly = 0.22f 50 ms ot over-temperature threshold 140 c i pg pg pull-down current vpg > 0.6v 15 a vpg < 0.6v 1.7 ma logic enable v hi logic high threshold 2.3 v v lo logic low threshold 0.8 v i low logic low bias current 0.2 2 a i high logic high bias current at v en = 5v 12 18 24 a note: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v dd = 5v, v boost = 11v, i load = 200ma, v on = 15v, v off = -5v, v logic = 2.5v, limits over -40c to +105c temperature range, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter description condition min (note 6) typ max (note 6) unit pin descriptions pin name pin number description 1, 2, 4, 6, 8, 10, 12, 16, 18, 23, 32 nc not connected 3 delb open drain output for gate drive of optional v boost delay fet 5 lx drain of the internal n-channel boost fet 7 drvp positive ldo base drive; open drain of an internal n-channel fet 9 fbp positive ldo voltage feedback input pin; regulates to 1.2v nominal 11 drvl logic ldo base drive; open drain of an internal n-channel fet 13 fbl logic ldo voltage feedback input pin; regulates to 1.2v nominal 14, 27 sgnd low noise signal ground 15 drvn negative ldo base drive; open drain of an internal p-channel fet 17 fbn negative ldo voltage feedback input pin; regulates to 0.2v nominal 19, 20, 21, 22 pgnd power ground, connected to source of internal n-channel boost fet 24 vref bandgap reference output voltage; bypass with a 0.1f to sgnd 25 cint v boost integrator output; connect capacitor to sgnd for pi-mode or connect to v dd for p-mode operation 26 fbb boost regulator voltage feedback i nput pin; regulates to 1.2v nominal 28 en enable pin; high = enable; low or floating = disable 29 vdd positive supply 30 pg push-pull gate drive of optional fault protection fet; when chip is disabled or when a fault has been detected, this is high 31 cdly a capacitor connected from this pin to sgnd sets the delay time for start-up sequence and sets the fault timeout time isl78010
5 fn6501.1 may 3, 2011 typical performance curves t a = +25c, unless otherwise specified. figure 1. v boost efficiency at v in =3v (pi-mode) figure 2. v boost efficiency at v in =5v (pi-mode) figure 3. v boost efficiency at v in = 3v (p-mode) figure 4. v boost efficiency at v in = 5v (p-mode) figure 5. v boost load regulation at v in =3v (pi-mode) figure 6. v boost load regulation at v in = 5v (pi-mode) i out (ma) efficiency (%) a vdd = 9v 0 100 200 300 400 100 80 60 40 20 0 a vdd = 15v a vdd = 12v 0 20 40 60 80 100 0 200 400 600 800 i out (ma) efficiency (%) a vdd = 12v a vdd = 9v a vdd = 15v 0 20 40 60 80 100 0 100 200 300 400 500 i out (ma) efficiency (%) a vdd = 9v a vdd = 12v a vdd = 15v 0 20 40 60 80 100 0 200 400 600 800 i out (ma) efficiency (%) a vdd = 12v a vdd = 9v a vdd = 15v -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 100 200 300 400 i out (ma) load regulation (%) a vdd = 9v a vdd = 15v a vdd = 12v 0 200 400 600 800 i out (ma) a vdd = 12v a vdd = 9v a vdd = 15v -1.0 -0.8 -0.6 -0.4 -0.2 0 load regulation (%) isl78010
6 fn6501.1 may 3, 2011 figure 7. v boost load regulation at v in = 3v (p-mode) figure 8. v boost load regulation at v in =5v (p-mode) figure 9. v boost line regulation (pi-mode) figure 10. v boost line regulation (p-mode) figure 11. v on load regulation figure 12. v off load regulation typical performance curves t a = +25c, unless otherwise specified. (continued) a vdd = 9v a vdd = 12v a vdd = 15v -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0 100 200 300 400 500 i out (ma) load regulation (%) 0 200 400 600 800 i out (ma) a vdd = 12v a vdd = 9v a vdd = 15v -5 -4 -3 -2 -1 0 load regulation (%) -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v in (v) line regulation (%) -2.5 -2.0 1.5 -1.0 -0.5 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v in (v) line regulation (%) load regulation (%) i out (ma) 0 -0.1 -0.3 -0.5 -0.6 0 20406080 -0.4 -0.2 load regulation (%) i out (ma) 0 -0.2 -0.8 -1.2 -1.4 020 6080100 -1.0 -0.6 40 -0.4 isl78010
7 fn6501.1 may 3, 2011 figure 13. v logic load regulation figure 14. start-up sequence figure 15. start-up sequence figure 16. start-up sequence figure 17. lx waveform - discontinuous mode figure 18. lx waveform - continuous mode figure 19. package power dissipation vs ambient temperature typical performance curves t a = +25c, unless otherwise specified. (continued) load regulation (%) i out (ma) 0 -0.2 -0.6 -1.0 -1.2 0 100 200 500 700 -0.8 -0.4 400 300 600 v cdly v ref v boost v logic time (10ms/div) c dly = 220nf v boost v logic v off v on time (10ms/div) c dly = 220nf time (10ms/div) c dly = 220nf v boost_delay v logic v off v on v in = 5v v out = 13v i out = 30ma time (400ns/div) v in = 5v v out = 13v i out = 200ma time (400ns/div) jedec jesd51-7 high effective thermal conductivity test board ambient temperature (c) power dissipation (w) 1.8 1.5 0.3 0 0.9 0 25 75 100 125 150 50 1.2 0.6 1.408w j a = 7 1 c / w t q f p ( 5 m m x 5 m m ) 0.282w isl78010
8 fn6501.1 may 3, 2011 applications information the isl78010 provides a highly integrated multiple output power solution for tft-lcd automotive applications. the system consists of one high efficiency boost converter and three linear-regulato r controllers (v on , v off , and v logic ) with multiple protection functi ons. a block diagram is shown in figure 20. table 1 lists the recommended components. the isl78010 integrates an n-channel mosfet boost converter to minimize external component count and cost. the a vdd , v on , v off , and v logic output voltages are independently set using external resistors. v on , v off voltages require external charge pumps which are post regulated using the int egrated ldo controllers. boost converter the main boost converter is a current mode pwm converter at a fixed frequency of 1mhz, which enables the use of low profile inductors and multi-la yer ceramic capa citors. this results in a compact, low cost power system for lcd panel design. the isl78010 is designed for continuous current mode, but it can also operate in discontinuous current mode at light load. in continuous current m ode, current flows continuously in the inductor during the en tire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. figure 21 shows the block diagram of the boost regulator. it uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comparator l ooks at the peak inductor current cycle by cycle and term inates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficienc y. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k is recommended. the boost converter output voltage is determined by equation 2: the current through the mosfet is limited to 2a peak. this restricts the maximum output current based on equation 3: where i l is peak to peak inductor ripple current, and is set by equation 4: where f s is the switching frequency. table 1. recommended typical application diagram components designation description c 1 , c 2 , c 3 10f, 16v x7r ceramic capacitor (1206) tdk c3216x7ric106m c 20 , c 31 4.7f, 25v x5r ceramic capacitor (1206) tdk c3216x5r1a475k d 1 1a, 20v low leakage schottky rectifier (case 457-04) on semi mbrm120et3 d 11 , d 12 , d 21 200ma, 30v schottky barrier diode (sot-23) fairchild bat54s l 1 6.8h, 1.3a inductor tdk slf6025t-6r8m1r3-pf q 1 -2.4, -20v p-channel 1.8v specified powertrench mosfet (supersot-3) fairchild fdn304p q 2 200ma, 40v npn amplifier (sot-23) fairchild mmbt3904 q 3 200ma, 40v pnp amplifier (sot-23) fairchild mmbt3906 q 4 -2a, -30v single p-channel logic level powertrench mosfet (supersot-3) fairchild fdn360p q 5 1a, 30v pnp low saturation amplifier (sot-23) fairchild fmmt549 a vdd v in --------------- - 1 1d ? ------------- = (eq. 1) a vdd r 1 r 2 + r 1 -------------------- - v ref = (eq. 2) i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- = (eq. 3) i l v in l --------- d f s ---- - = (eq. 4) isl78010
9 fn6501.1 may 3, 2011 figure 20. block diagram pwm logic controller buffer oscillator slope compensation osc reference generator vref gm amplifier uvlo comparator voltage amplifier current amplifier thermal shutdown ss + - uvlo comparator buffer uvlo comparator uvlo comparator ss + - en + - buffer shutdown and start-up control buffer fbp drvl fbl drvp fbb cint drvn fbn 0.4v 0.2v vref vref comp current limit comparator current ref pgnd lx sgnd vdd pg cdly delb en isl78010
10 fn6501.1 may 3, 2011 figure 21. block diagram of the boost regulator iref iref fbb ifb ifb cint voltage amplifier lx pgnd shutdown and startup control gm amplifier slope compensation buffer pwm logic current amplifier clock reference generator isl78010
11 fn6501.1 may 3, 2011 table 2 gives typical values (margins are considered 10%, 3%, 20%, 10%, and 15%) on v in , v o , l, f s , and i omax . input capacitor an input capacitor is used to supply the peak charging current to the converter. it is recommended that c in be larger than 10f. the reflected ripple voltage will be smaller with larger c in . the voltage rating of the input capacitor should be larger than the maximum input voltage. boost inductor the boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. values of 3.3h to 10h are to match the internal slope compensation. the inductor must be able to handle the following average (equation 5) and peak (equation 6) current: rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the rectifier diode must meet the output current and peak inductor current requirements. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging an d discharging of the output capacitor (equation 7). for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in equation 7 assumes the effective value of the capacitor at a particular voltage and not the manu facturer?s stated value, measured at zero volts. compensation the isl78010 can operate in either p-mode or pi-mode. p-mode may be preferred in applications where excellent transient load performance is required but regulation is not critical. connecting the cint pin directly to v in will enable p-mode; for better load regulati on, use pi-mode with a 4.7nf capacitor in series with a 10 k resistor betw een cint and ground. this value may be reduced to improve transient performance; however, very low values will reduce loop stability. figures 5 through 10 show a comparison of p-mode vs pi-mode performance. boost feedback resistors as the boost output voltage, a vdd , is reduced below 12v, the effective voltage feedback in the ic increases the ratio of voltage to current feedback at the summing comparator because r 2 decreases relative to r 1 . to maintain stable operation over the complete current range of the ic, the voltage feedback to the fbb pin should be reduced proportionally, as a vdd is reduced. this can be accomplished by means of a series resistor-capacitor network (r 7 and c 7; equations 8 and 9) in parallel with r 1 , with a pole frequency (f p ) set to approximately 10khz for c 2 (effective) = 10f and 4khz for c 2 (effective) = 30f. pi-mode c int (c 23 ) and r int (r 10 ) the ic is designed to operate with a minimum c 23 capacitor of 4.7nf and a minimum c 2 (effective) = 10f. note that, for high voltage a vdd , the voltage coefficient of ceramic capacitors (c 2 ) reduces their effective capacitance greatly; a 16v, 10f ceramic can drop to around 3f at 15v. to improve the transie nt load response of a vdd in pi-mode, a resistor may be added in series with the c 23 capacitor. the larger the resistor, the lower the overshoot, but at the expense of stability of the converter loop, especially at high currents. with l = 10h, a vdd = 15v, and c 23 = 4.7nf, c 2 (effective) should have a capacitance of greater than 10f. r int (r 7 ) can have values up to 5k for c 2 (effective) up to 20f and up to 10k for c 2 (effective) up to 30f. table 2. typical v in , v o , l, f s , and i omax values v in (v) v o (v) l ( h) f s (mhz) i omax (a) 3.3 9 6.8 1 0.490686 3.3 12 6.8 1 0.307353 3.3 15 6.8 1 0.197353 5 9 6.8 1 0.743464 5 12 6.8 1 0.465686 5 15 6.8 1 0.29902 i lavg i o 1d ? ------------- = (eq. 5) i lpk i lavg i l 2 -------- + = (eq. 6) v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- - + = (eq. 7) r 7 1 0.1 r 2 --------------------- - ?? ?? 1 r 1 ------ - ? ?? ?? 1 ? = (eq. 8) c 7 1 2 3.142 f p r 7 ------------------------------------------------- = (eq. 9) isl78010
12 fn6501.1 may 3, 2011 larger values of r int (r 7 ) may be possible if maximum a vdd load currents less than the current limit are used. to ensure a vdd stability, the ic should be operated at the maximum desired current and then the transient load response of a vdd should be used to determine the maximum value of r int . operation of the delb output function an open drain delb output is provided to allow the boost output voltage, developed at c 2 (see ?typical application diagram? on page 18), to be delayed via an external switch (q 4 ) to a time after the v boost supply and negative v off charge pump supply have achieved regulation during the start-up sequence shown in figures 14 and 16. this then allows the a vdd and v on supplies to start-up from 0v instead of the normal offset voltage of v in -v diode (d 1 ) if q 4 were not present. when delb is activated by the start-up sequencer, it sinks 50a, allowing a controlled turn-on of q 4 and charge-up of c 9 . c 16 can be used to contro l the turn-on time of q 4 to reduce in-rush current into c 9 . the potential divider formed by r 9 and r 8 can be used to limit the v gs voltage of q 4 if required by the voltage rating of this device. when the voltage at delb falls to less than 0.6v, the sink current is increased to ~1.2ma to firmly pull delb to 0v. the voltage at delb is monitored by the fault protection circuit so that if the initial 50a sink current fails to pull delb below ~0.6v after the start-up sequencing has completed, then a fault condition will be det ected and a fault time-out ramp will be initiated on the c del capacitor (c 7 ). operation of the pg output function the pg output consists of an internal pull-up pmos device to v in , to turn off the external q 1 protection switch, and a current-limited pull-down nmos device which sinks ~15a, allowing a controlled turn-on of q 1 gate capacitance. c o is used to control how fast q 1 turns on and limiting inrush current into c 1 . when the voltage at the pg pin falls to less than 0.6v, the pg sink current is increased to ~1.2ma to firmly pull the pin to 0v. the voltage at pg is monitored by the fault protection circuit so that if the initial 15a sink current fails to pull pg below ~0.6v after the start-up sequencing has completed, then a fault condition will be detected, and a fault time-out ramp will be initiated on the c del capacitor (c 7 ). cascaded mosfet application a 20v n-channel mosfet is integrated in the boost regulator. for applications where the output voltage is greater than 20v, an external cascaded mosfet is needed as shown in figure 22. the voltage rating of the external mosfet should be greater than v boost . linear-regulator controllers (v on , v logic , and v off ) the isl78010 includes three independent linear-regulator controllers, in which two ar e positive output voltage (v on and v logic ) and one is negative. the v on , v off , and v logic linear-regulator controller functional diagrams are shown in figures 23, 24, and 25, respectively. calculation of the linear regulator base-emitter resistors (r bl , r bp and r bn ) for the pass transistor of the linear regulator, low frequency gain (h fe ) and unity gain frequency (f t ) are usually specified in the datasheet. the pass transistor adds a pole to the loop transfer function at f p =f t /h fe . therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high-frequency, low-gain switching transistor. further improvement can be obtained by adding a base-emitter resistor r be (r bp , r bl , r bn in the functional block diagrams on page 13), which increase the pole frequency to f p =f t *(1+ h fe *re/r be )/h fe , where re = kt/qic. choose the lowest value r be in the design as long as there is still enough base current (i b ) to support the maximum output current (i c ). for example, if in the v logic linear regulator, a fairchild fmmt549 pnp transistor is used as the external pass transistor (q 5 in the application diagram), then for a maximum v logic operating requirement of 500ma, the data sheet indicates h fe (min) = 100. the base-emitter saturation voltage is vbe_max = 1.25v. note that this is normally vbe ~ 0.7v; however, for the q 5 transistor, an internal darlington arrangement is used to increase its current gain, giving a ?base-emitter? voltage of 2xv be . note also that using a high current darlington pnp transistor for q 5 requires that v in > v logic + 2v. should a lower input voltage be required, then an ordinary high-gain pnp transistor should be selected for q 5 to allow a lower collector-emitter saturation voltage. isl78010 fb lx v boost v in figure 22. cascaded mosfet topology for high output voltage applications isl78010
13 fn6501.1 may 3, 2011 for the isl78010, the minimum drive current is as shown in equation 10: the minimum base-emitter resistor, r bl , can now be calculated as shown in equation 11: this is the minimum value that can be used. choose a convenient value greater than this minimum value; for example, 500 . larger values may be used to reduce quiescent current; however, regulation may be adversely affected by supply noise if the value of r bl is too high. figure 23. v on functional block diagram figure 24. v off functional block diagram figure 25. v logic functional block diagram the v on power supply is used to power the positive supply of the row driver in the lcd pa nel. the dc/dc consists of an external diode-capacitor charge pump powered from the inductor (lx) of the boost converter, followed by a low dropout linear regulator (ldo_on). the ldo_on regulator uses an external pnp transistor as the pass element. the on-board ldo controller is a wide band (>10mhz) transconductance amplifier capable of 4ma drive current, which is sufficient for up to 40ma or more output current under the low dropout condition (forced beta of 10). typical v on voltage supported by the isl78010 ranges from +15v to +36v. a fault comparator is also included for monitoring the output voltage. the undervo ltage threshold is set at 25% below the 1.2v reference. the v off power supply is used to power the negative supply of the row driver in the lcd panel. the dc/dc consists of an external diode-capacitor charge pump powered from the inductor (lx) of the boost converter, followed by a low dropout linear regulator (ldo_off). the ldo_off regulator uses an external npn transistor as the pass element. the on-board ldo controller is a wide band (>10mhz) transconductance amplifier capable of 4ma drive current, which is sufficient for up to 40ma or more output current under the low dropout co ndition (forced beta of 10). typical v off voltage supported by the isl78010 ranges from -5v to -20v. a fault comparator is also included for monitoring the output voltage. the undervoltage threshold is set at 200mv above the 0.2v reference level. the v logic power supply is used to power the logic circuitry within the lcd panel. the dc/dc may be powered directly from the low voltage input, 3.3v or 5.0v, or it may be powered through the fault protection switch. the ldo_logic regulator uses an external pnp transistor as the pass element. the on-board ldo controller is a wide band (>10mhz) transconductance amplifier capable of 16ma drive current, which is sufficient for up to 160ma or i drvl min () 8ma = (eq. 10) r bl min () v be max () i drvl min () i c h fe min () ? ? () = ? = (eq. 11) 1.25v 8ma 500ma 100 ? ? () ? 417 = - + - + 36v esd clamp gmp ldo_on pg_ldop 1: np fbp drvp 7k r bp v boost 0.1f 0.1f cp (to 36v) 20k r p2 r p1 c on v on (to 35v) lx 0.9v q3 - + - + 36v esd clamp gmn ldo_off 1: nn fbn drvn 0.1f 0.1f cp (to -26v) r bn c off v off (to -20v) 3k lx r n1 r n2 20k v ref pg_ldon 0.4v q2 - + - + gml ldo_log pg_ldol 1: n1 fbl drvl v in or v prot (3v to 6v) 20k r l2 r l1 c log v logic (1.3v to 3.6v) 0.9v 10f 500 r bl q5 isl78010
14 fn6501.1 may 3, 2011 more output current under the low dropout condition (forced beta of 10). typical v logic voltage supported by the isl78010 ranges from +1.3v to v dd - 0.2v. a fault comparator is also included for monitoring the output voltage. the undervoltage threshold is set at 25% below the 1.2v reference. set-up output voltage as shown in the ?typical application diagram? on page 18, the output voltages of v on , v off , and v logic are as determined by equations 12, 13 and 14: where v ref = 1.2v and v refn = 0.2v. resistor networks in the order of 250k , 120k and 10k are recommended for v on , v off and v logic , respectively. charge pump to generate an output voltage higher than v boost , single or multiple stages of charge pumps are needed. the number of stages is determined by the input and output voltage. use equation 15 to calculate positive charge pump stages: where v ce is the dropout voltage of the pass component of the linear regulator. it ranges from 0.3v to 1v depending on the transistor. v f is the forward-voltage of the charge pump rectifier diode. the number of negative charge pump stages is given by equation 16: to achieve high efficiency and low material cost, the lowest number of charge pump stages that can meet the above requirements is preferred. high charge pump output voltage (>36v) applications in applications where the charge pump output voltage is over 36v, an external npn transistor must be inserted between the drvp pin and the base of pass transistor q 3 as shown in figure 26, or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in figure 27. discontinuous/continuous boost operation and its effect on the charge pumps the isl78010 v on and v off architecture uses lx switching edges to drive diode charge pumps from which ldo regulators generate the v on and v off supplies. should a regular supply of lx switching edges be interrupted - for example, during discontinuous operation at light a vdd boost load currents - it may affect the performance of v on and v off regulation, depending on their exact loading conditions at the time. to optimize v on /v off regulation, the boundary of discontinuous/continuous operat ion of the boost converter can be adjusted, by suitable choice of inductor (given v in , v out , switching frequency and the a vdd current loading), to be in continuous operation. v on v ref 1 r 12 r 11 --------- - + ?? ?? ?? = (eq. 12) v off v refn r 22 r 21 --------- - v refn v ref ? () + = (eq. 13) v logic v ref 1 r 42 r 41 --------- - + ?? ?? ?? = (eq. 14) n positive v out v ce v input ? + v input 2v f ? ------------------------------------------------------------- - (eq. 15 ) n negative v output v ce + v input 2v f ? ------------------------------------------------ - (eq. 16) v in or a vdd charge pump output 7k q3 fbp drvp npn cascode transistor v on figure 26. cascode npn transistor configuration for high charge pump output voltage (>36v) isl78010 v on (>36v) 0.1f 0.1f 0.1f 0.1f 7k 0.47f 0.22f 0.1f a vdd lx q3 fbp isl78010 drvp figure 27. the linear regulator controls one stage of charge pump isl78010
15 fn6501.1 may 3, 2011 equation 17 gives the boundary between discontinuous and continuous boost operation. continuous operation (lx switching every clock cycle) requires: where the duty cycle, d = (a vdd - v in )/a vdd for example, with v in = 5v, f osc = 1.0mhz and a vdd = 12v, continuous operation of the boost converter can be guaranteed as shown in equations 18, 19, and 20: charge pump output capacitors ceramic capacitors with lo w esr are recommended. with ceramic capacitors, the output ripple voltage is dominated by the capacitance value. the capacitance value can be calculated as shown in equation 21: where f osc is the switching frequency. start-up sequence figure 28 shows a detailed start-up sequence waveform. for a successful power-up, there should be six peaks at v cdly . when a fault is detected, the device will latch off until either en is toggled or the input supply is recycled. when the input voltage is higher than 2.5v, an internal current source starts to charge c cdly to an upper threshold using a fast ramp followed by a slow ramp. during the initial slow ramp, the device che cks whether there is a fault condition. if no fault is found, c cdly is discharged after the first peak, and v ref turns on. during the second ramp, the device checks the status of v ref and over-temperature. at the peak of the second ramp, pg output goes low and enables the input protection pmos q 1 . q 1 is a controlled fet used to prevent in-rush current into v boost before v boost is enabled internally. its rate of turn-on is controlled by c o . when a fault is detected, m1 will turn off and disconnect the inductor from v in . with the input protection fet on, node1 (see ?typical application diagram? on page 18) will rise to ~v in . initially the boost is not enabled, so v boost rises to v in -v diode through the output diode. he nce, there is a step at v boost during this part of the start-up sequence. if this step is not desirable, an external p-mosfet can be used to delay the output until the boost is enabled internally. the delayed output appears at a vdd . v boost soft-starts at the beginning of the third ramp. the soft-start ramp depends on the value of the c dly capacitor. for c dly of 220nf, the soft-start time is ~2ms. v ref and v logic turn on when input voltage (v dd ) exceeds 2.5v. when a fault is detected, the outputs and the input protection will turn off but v ref will stay on. v off turns on at the start of the fourth peak. at the fifth peak, the open drain o/p delb goes low to turn on the external pmos q 4 to generate a delayed v boost output. v on is enabled at the beginning of the sixth ramp. a vdd , pg, v off , delb and v on are checked at end of this ramp. fault protection during the start-up sequence, prior to boost soft-start, v ref is checked to be within 20% of its final value, and the device temperature is checked. if either of these is not within the expected range, the part is disabled until the power is recycled or en is toggled. if c delay is shorted low, then the sequence will not start, while if c delay is shorted h, the first down ramp will not occur and the sequence will not complete. once the start-up sequence is completed, the chip continuously monitors c dly , delb, fbp, fbl, fbn, v ref , fbb, and pg, and checks for faults. during this time, the voltage on the c dly capacitor remains at 1.15v until either a fault is detected or the en pin is pulled low. a fault on c delay , v ref , or temperature will shut down the chip immediately. if a fault on any other output is detected, c delay will ramp up linearly with a 5a (typical) current to the upper fault threshold (typical ly 2.4v), at which point the chip is disabled unt il the power is recycled or en is toggled. if the fault condition is removed prior to the end of the ramp, the voltage on the c dly capacitor returns to 1.15v. typical fault thresholds for fbp, fbl, fbn, and fbb are included in the ?electrical specifications? table beginning on page 2. pg and delb fault thresholds are typically 0.6v. c int has an internal current-limited clamp to keep the voltage within its normal range. if c int is shorted low, the boost regulator will attempt to regulate to 0v. if c int is shorted h, the regulator switches to p mode. if any of the regulated outputs (v boost , v on , v off or v logic ) are driven above their ta rget levels, the drive circuitry will switch off until the output returns to its expected value. i avdd load () d1d ? () v in > 2lf osc -------------------------------------------------------------------------------------- - (eq. 17) l10 h and i avdd 61ma > = (eq. 18) l6.8 h and i avdd 89ma > = (eq. 19) l3.3 h and i avdd 184ma > = (eq. 20) c out i out 2v ripple f osc ------------------------------------------------------ (eq. 21) isl78010
16 fn6501.1 may 3, 2011 v cdly en v ref v boost v logic v off delayed v boost v on pg on a vdd soft-start v off on delb on v on soft-start fault detected chip disabled normal operation fault present start-up sequence timed by c dly v ref , v logic on t os t on t del1 v in t del3 t del2 figure 28. start-up sequence isl78010
17 fn6501.1 may 3, 2011 if v boost is excessively loaded, the current limit will prevent damage to the chip. while in current limit, the part acts like a current source, and the regulated output will drop. if the output drops below the fault threshold, a ramp will be initiated on c delay and, provided the fault is sustained, the chip will be disabled upon completion of the ramp. in some circumstances (depend ing on ambient temperature and thermal design of the boa rd), continuous operation at current limit may result in the over-temperature threshold being exceeded, which will c ause the part to disable immediately. all i/o also has esd protection, which in many cases will also provide overvoltage protection relative to either ground or vdd. however, these wi ll not generally operate unless absolute maximum ratings are exceeded. component selection for start-up sequencing and fault protection the c ref capacitor is typically set at 220nf and is required to stabilize the v ref output. the range of c ref is from 22nf to 1f and should not be more than five times the capacitor on c del to ensure correct start-up operation. the c del capacitor is typically 220nf and has a usable range from 47nf minimum to several microfarads. it is limited only by leakage in the capacitor reaching a levels. c del should be at least 1/5 of the value of c ref . note that with 220nf on c del the fault time-out will typically be 50ms, and the use of a larger or smaller value will vary this time proportionally (e.g., 1f will gi ve a fault time-out period of typically 230ms). fault sequencing the isl78010 has adv anced fault detection systems which protect the ic from both adjacent pin shorts during operation and shorts on the output supplies. a high-quality layout and desig n of the pcb with respect to grounding and decoupling is necessary to avoid falsely triggering the fault detection scheme, especially during start-up. see ?layout recommendation? on page 17 and ?component selection for start-up sequencing and fault protection? on page 17 to avoid problems during initial evaluation and protot ype pcb generation. over-temperature protection an internal temperature sens or continuously monitors the die temperature. if the die te mperature exceeds the thermal trip point of +140c, the device will shut down. layout recommendation device performance, including efficiency, output noise, transient response and control loop stability, is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. some general guidelines for layout include: 1. place the external power components (the input capacitors, output capacitors , boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v ref and v dd bypass capacitors close to the pins. 3. minimize the length of trac es carrying fast signals and high current. 4. all feedback networks shoul d sense the output voltage directly from the point of load, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at only one point near the main decoupling capacitors. 6. a signal ground plane, separate from the power ground plane, should be used for ground return connections for feedback resistor networks (r 1 , r 11 , r 41 ) and the v ref capacitor, c 22 ; the c delay capacitor, c 7 ; and the integrator capacitor, c 23 . 7. minimize feedback input track lengths to avoid switching noise pickup. 8. connect all "nc" pins to the ground plane to improve thermal performance and switching noise immunity between pins. an evaluation board, ISL78010EVAL1Z , is available to illustrate the proper layout implementation. see ?ordering information? on page 1. isl78010
18 fn6501.1 may 3, 2011 typical application diagram note: sgnd should be connected to pgnd at one point only. lx fbb delb cint drvp fbp drvn fbn pgnd pg cdelay vdd en vref drvl fbl sgnd v in c 10 4.7f node 1 v logic (2.5v) c 31 4.7f c 41 0.1f r 43 500 c 22 0.1f r 42 5.4k r 41 5k r 7 10k v ref c 6 4.7f r 6 10 c 7 0.22f q 1 c 0 1nf c 1 10f x2 node 1 l 1 6.8h lx d 1 r 2 46.5k r 1 5k c 2 -c 3 10f r 9 1m c 16 22nf c 9 0.1f r 8 10k a vdd (12v) c 23 4.7nf c p 1nf r 13 7k q 3 c 14 0.1f c 15 0.47f r 11 20k r 12 230k r 23 3k r 22 104k c 20 4.7f r 21 20k c 25 0.1f d 21 c 12 0.1f d 12 d 11 c 24 0.1f q 2 c 13 0.1f c 11 0.1f v on (15v) v off (-5v) lx lx v ref q 5 q 4 x2 r 7 open c 7 open r 10 10k * * * * * isl78010
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6501.1 may 3, 2011 isl78010 thin plastic quad fl atpack packages (tqfp) d d1 e e1 -a- pin 1 a2 a1 a 11 o -13 o 11 o -13 o 0 o -7 o 0.020 0.008 min l 0 o min plane b 0.004/0.008 0.09/0.20 with plating base metal seating 0.004/0.006 0.09/0.16 b1 -b- e 0.003 0.08 a-b s d s c m 0.08 0.003 -c- -d- -h- 0.25 0.010 gage plane q32.5x5 (jedec ms-026aaa issue b) 32 lead thin plastic quad flatpack package symbol millimeters notes min max a - 1.20 - a1 0.05 0.15 - a2 0.95 1.05 - b 0.17 0.27 6 b1 0.17 0.23 - d 6.90 7.10 3 d1 4.90 5.10 4, 5 e 6.90 7.10 3 e1 4.90 5.10 4, 5 l 0.45 0.75 - n327 e0.50 bsc - rev. 0 2/07 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toleranc es per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. ?n? is the number of terminal positions. -c- -h-

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